The relentless arms race surrounding custom artificial intelligence chips approaches a critical hardware architecture turning point. A recent report from the prominent semiconductor analysis firm SemiAnalysis reveals intriguing details. Currently, Google is purportedly engaged in a highly confidential collaboration with AMD. Together, they are jointly developing a specific chip initiative within the forthcoming 10th-generation Tensor Processing Unit (TPU) family.
If researchers substantiate this information, it represents a momentous milestone. This partnership would mark AMD’s inaugural, profound foray into the custom AI Application-Specific Integrated Circuit (ASIC) domain. More importantly, it strongly suggests an impending, fundamental transformation in future AI computing architectures. This shift is primarily driven by the rapid ascendancy of reinforcement learning and sophisticated agentic AI models. For deeper industry insights, you can review analysis discussing how Google and AMD collaborate on custom AI silicon on social media.
Reinforcement Learning Shifts the Compute Balance
The Resurgence of the CPU
Historically, the training phases for generative AI and massive language models relied almost exclusively on specialized processors like GPUs or TPUs. Conversely, the central processing unit (CPU) relegated itself to merely a foundational scheduling role. However, SemiAnalysis astutely points out a shifting paradigm. The industry focus is gravitating heavily toward inference models, autonomous AI agents, and reinforcement learning paradigms requiring intense logical decision-making. Consequently, these models demand colossal general-purpose CPU computing resources. They require this power to handle complex data and intricate logical scheduling precisely before and after executing intensive accelerator computations.
Observing the Architectural Evolution
We can clearly observe this compelling trend toward increased CPU compute allocation by analyzing the evolution of Google’s server architecture. Within servers deploying the 7th-generation TPU, Google utilized a specific ratio: four TPUs paired with a single Intel Xeon processor (utilizing the Emerald Rapids architecture). However, the latest TPU 8i systems, engineered specifically for inference and reinforcement learning, display a dramatic shift. This ratio has intensified significantly; every two TPUs now necessitate pairing with one proprietary Google Axion CPU.
During a recent visit to Taiwan, AMD CEO Lisa Su accurately forecasted this exact market trajectory. She emphasized that as agentic AI technologies mature rapidly, future AI computing nodes will transition “very soon.” They will adopt a symmetrical architecture featuring one GPU (or accelerator) paired directly with one CPU. This bold prediction implies that data center demand for high-performance CPUs over the next five years will vastly exceed current market expectations.
Why Google Chose AMD over Broadcom
Seeking Advanced Packaging and CPU IP
Industry experts widely know that Google traditionally collaborated with Broadcom for the backend physical chip design and ASIC netlist conversion across multiple prior TPU generations. Considering Google has amassed profound experience in proprietary TPU architecture, why did they actively seek AMD for the critical 10th-generation TPU project?
Industry analysts speculate that Google does not expect AMD to directly engineer the core tensor processing units for the TPU v10i (inference) or v10t (training). Instead, Google intensely values the comprehensive intellectual property portfolio AMD possesses. This portfolio includes potent x86 CPU IP, advanced chiplet interconnect technologies, programmable logic device expertise (derived from Xilinx), and formidable SoIC advanced packaging capabilities.
Overcoming I/O Bottlenecks
Theoretically, integrating general-purpose computing units (CPUs) and tensor processing units (TPUs) directly within the identical chip package minimizes data transfer latency drastically. Furthermore, it significantly reduces the inherent power consumption associated with complex data transmission. For reinforcement learning workloads, which demand exceptionally high I/O transmission bandwidth, this deep integration represents the critical key to shattering existing performance bottlenecks.
The MI300A Success Secures the Deal
A Proven Track Record in Advanced Integration
If Google ultimately decides to pursue the complex path of co-packaging “TPU + CPU + HBM” (High Bandwidth Memory), AMD stands alone in the current semiconductor market. AMD remains arguably the only chip manufacturer possessing extensive, successful mass-production experience with this specific architectural methodology.
The AMD Instinct MI300A accelerator, designed explicitly for high-performance data centers, serves as a masterclass in integration. It flawlessly combines x86 CPU cores, GPU accelerator chiplets, and high-bandwidth memory within a single, unified package. Industry insiders playfully refer to this architecture as a “giant APU.” Crucially, this specific engineering experience perfectly embodies the optimal blueprint Google desperately wishes to replicate for its next-generation TPU.
While Intel undeniably possesses formidable x86 architecture and maintains a deep, historical relationship with Google, it currently lacks comparable real-world experience. Regarding similar data-center-grade, advanced packaging products that tightly integrate CPUs and accelerators, Intel cannot yet match the mature, proven firepower of the MI300A.
Reshaping the Custom Chip Battlefield
The Power of a Comprehensive IP Portfolio
We can extract a vital industry signal from this compelling rumor: pure “accelerator design foundry” services can no longer satisfy the insatiable future appetites of cloud computing giants. As AI models evolve rapidly, simply stacking Multiply-Accumulate (MAC) computing power is entirely insufficient. The defining future challenge lies in definitively resolving the severe bandwidth and latency issues inherent in heterogeneous computing.
AMD uniquely leverages a profound technical foundation spanning both high-performance CPUs and GPUs. When combined with the advanced packaging and robust interconnect technologies acquired through the Xilinx merger, AMD boasts an unparalleled “system-level IP combo.” This comprehensive package grants them a massive advantage when competing for custom chip orders from major cloud providers. It is an offering that competitors like Broadcom, Marvell, and even MediaTek cannot currently match.
A Potential Paradigm Shift
If AMD successfully utilizes the Google TPU project to forcefully open the door to custom AI ASICs, it signifies a massive triumph. This achievement would not merely represent another significant milestone for AMD’s burgeoning data center business. More importantly, it could easily trigger other cloud computing titans, such as Microsoft and Meta, to reconsider their strategies. When planning their future proprietary chips, they might seriously evaluate the distinct possibility of initiating deep architectural licensing collaborations directly with AMD.
Support Our Threat Intelligence
If you find our technology report and cybersecurity news helpful, consider supporting our work.
Buy Me a Coffee
PayPal
