The race to build massive artificial intelligence processors has hit an unexpected wall. New ASML lithography machines can print significantly smaller elements. However, the largest accelerators from Nvidia and other developers physically exceed the available exposure field.
The High NA EUV Dilemma
This critical issue stems from the new High NA EUV generation. These advanced ASML systems increase the numerical aperture from 0.33 to 0.55. Consequently, they can form intricate elements with a stunning 8-nanometer resolution. According to the manufacturer, this technology creates structures 1.7 times smaller in a single pass. Furthermore, it places roughly 2.9 times more transistors than current NXE EUV systems.
Unfortunately, this increased precision required a complete optical redesign. High NA systems utilize anamorphic mirrors. As a result, the exposure field shrank by approximately half. Standard EUV machines can produce silicon dies measuring around 800 square millimeters. Developers like Nvidia and Google have already approached this absolute limit. Therefore, these new machines cannot transfer such a massive pattern onto a wafer in one piece.
Stitching Challenges and the 12-Inch Solution
Manufacturers could split a massive die into several distinct regions. Then, they could precisely align them during consecutive exposures. However, this “stitching” method complicates production heavily. It reduces equipment throughput and introduces severe alignment error risks. This physical limitation becomes particularly painful for AI accelerators. In these designs, developers strive to utilize nearly every millimeter of available die space.
ASML and TSMC proposed a bold solution to this looming crisis. They want to transition from current 6-inch photomasks to massive 12-inch versions. You can read more about TSMC advancing mask technology directly. This larger format should restore the ability to expose giant dies without stitching. At the same time, it preserves the incredible benefits of High NA. Other major chipmakers and equipment suppliers have also expressed deep interest in this vital initiative. Additionally, ASML will work with major chipmakers to use the latest tools for larger chips.
Industry Adoption Timelines
High NA technology has already left the research laboratories. Intel currently uses ASML equipment to manufacture specific layers of Core Ultra Series 3 processors. They achieve this using the advanced Intel 18A process node. Meanwhile, TSMC expects to utilize High NA for mass production on cutting-edge nodes starting in 2030. Samsung plans to implement this technology for DRAM memory by 2028. Similarly, SK Hynix is targeting an identical timeframe.
Rebuilding the Manufacturing Ecosystem
Transitioning to enlarged photomasks requires rebuilding the entire manufacturing ecosystem completely. This massive overhaul includes the masks themselves and the equipment for manufacturing them. It also impacts inspection tools, transportation systems, and the core lithography machines. Therefore, this will definitely not be a quick fix. ASML expects to launch a pilot line for the new format by 2031. Subsequently, they plan to prepare mass production equipment by 2033.
Fortunately, the final payoff could be truly remarkable. ASML executive Marco Pieters expects a 40 percent throughput increase after adopting larger masks. For semiconductor fabs, a single High NA EUV machine costs hundreds of millions of euros. Thus, such a massive performance boost directly lowers the production cost of every single chip.
The Shifting Global Chip Race
This historical development perfectly illustrates the newest problem in the semiconductor industry. Engineers can still shrink individual transistors successfully. However, AI demands increasingly larger processor dies simultaneously. As a result, future progress depends on more than just shrinking nanometers. It heavily relies on how large a pattern the lithography machine can transfer onto silicon in a single pass.
Just this past spring, TSMC decided against rushing High NA adoption. The astronomical cost of these new systems does not always justify the performance gains yet. Now, the 12-inch photomask roadmap shows how this technology might become economically viable for the largest contract chipmaker. In contrast, Intel began preparing for this new lithography generation far earlier than its fierce competitors. The company links High NA EUV directly to its future Intel 14A process node. They plan to combine this precise printing with novel RibbonFET transistors and PowerVia backside power delivery.
Concurrently, EUV lithography is no longer exclusively a Western technology. In late 2025, reports revealed a Chinese EUV prototype machine. Engineers created this system despite years of severe export restrictions. This Chinese equipment remains far behind the capabilities of commercial ASML machines today. Nevertheless, the strategic importance of lithography in the global chip race continues to grow exponentially.
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